Open the schematic document Simple_Counter.SchDoc.Let's go ahead and capture the clock division circuitry in a schematic sub-sheet. Clock Division using a Schematic Sub-Sheet Rather than adding this circuitry to the Simple_Counter schematic, we will capture it in a sub-file (first in a schematic and then in a VHDL file), to demonstrate how hierarchical designs can be used when programming an FPGA. To slow down the counter we will add clock division circuitry. In the base design for our simple counter example, we saw that the synchronous clock signal sourced from the Desktop NanoBoard was too fast. Hierarchical net connectivity is from the sheet entries to matching ports on the document below. Hierarchical net and bus connectivity between documents obeys the standard hierarchical project connection behavior, where ports on the sub-document connect to sheet entries of the same name in the sheet symbol that represents that document, as shown for schematic and VHDL sub-documents in Figure 1.įigure 1. Using this approach a design hierarchy of any depth or complexity can be created. This underlying file can be:Ī schematic sub-sheet can also include sheet symbols referencing lower design files. The Filename attribute of each sheet symbol references the underlying design file that it represents. In a hierarchical design, the design is partitioned into logical blocks, with each block represented on the top schematic sheet by a sheet symbol. While the FPGA project file ( *PrjFpg) links the various source documents into a single project, the document-to-document and net connective relationships are defined by information in the documents themselves.
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